In recent years, a semiconductor memory device which uses nonvolatile memory cells each composed of a vertical transistor has been proposed. In this device, a control gate electrode layer (or a word line electrode layer) and an interlayer insulating film (or an inter-word-line insulating film layer) are deposited alternately and horizontally on the surface of a silicon substrate. In the stacked structure part, a trench is made in a direction perpendicular to the silicon substrate surface and a vertical transistor with an electrically-insulated charge storage layer is formed in the trench. This enables a high-density memory cell structure to be realized.
However, this type of device has the following problem: charge storage layers are connected between memory cells vertically adjacent to one another, permitting cell storage charges to move into adjacent cells, which deteriorates the charge retention characteristic. Unlike an ordinary memory cell structure, it is very difficult to isolate charge storage layers between adjacent cells in a memory cell structure which uses vertical transistors.